About ReviveSparc

History

The OpenSPARC project was launched by Sun Microsystems in 2006, releasing the UltraSPARC T1 and T2 processor designs as open-source hardware. The accompanying software — simulators, verification suites, and firmware — was released under the GPL. However, parts of the codebase originated from AT&T Unix source code, creating licensing uncertainty that prevented widespread adoption by the open-source community.

ReviveSparc was started in early 2026 to address this. By rebuilding everything from the published ISA specification — without reference to the original source code — we provide a legally clean, fully open-source implementation.

Clean Room Process

We follow a strict clean-room methodology:

• Developers working on the implementation have no access to the original OpenSPARC source code.
• Only publicly available specification documents are used: the SPARC Architecture Manual v9, the UltraSPARC T1 Supplement, and the OpenSPARC specification.
• All new code is written from scratch, with no derived or translated code from the original project.
• The resulting code is licensed under the BSD 2-Clause License, permitting both open-source and proprietary use.

Project Goals

• Full SPARC V9 ISA compliance — user and privileged instructions, including VIS (Visual Instruction Set) extensions.
• Multi-core simulation — support for chip-multithreading (CMT) as in the original T1/T2 designs.
• Boot real operating systems — Linux, NetBSD, OpenBSD, and potentially Solaris.
• Hardware implementation path — provide a Verilog RTL target for FPGA prototyping.
• Educational resource — serve as a clean reference for students and researchers studying processor architecture.

Architecture Overview

ReviveSparc targets the UltraSPARC architecture profile:

Feature	Description
ISA	SPARC V9 (with VIS 1/2 extensions)
Pipeline	6-stage, in-order, dual-issue
Threading	4 threads per core (fine-grained CMT)
Cores	1 to 8
MMU	SPARC Reference MMU with TLB
Cache	Split I/D L1, unified L2
Interrupts	UltraSPARC-style interrupt controller

Repository Structure

revivesparc/
  emu/         -- Functional instruction-set simulator
  rtl/         -- Verilog RTL for synthesis
  soft/        -- Firmware and boot ROM code
  tests/       -- ISA verification test suite
  tools/       -- Helper scripts and utilities
  docs/        -- Additional documentation

ReviveSparc is released under the BSD 2-Clause License.